Planar complementary metal-oxide silicon (CMOS) transistors may be desirable in circuit structures for many reasons. Such transistors may, for example, provide fully depleted planar devices, superior short channel control, low junction leakage current, and other advantages. As circuit structure sizes continue to shrink, scaling of CMOS transistors to smaller sizes may require novel fabrication techniques to achieve expected high performance levels without losing the advantages of the planar transistor architecture.